Zilog, Inc Z32F3841 2025.07.02 Z32F3841, ARM 32-bit Cortex-M3 Microcontroller based device. CM3 r2p0 little 3 false 8 32 AD0 12-BIT A/D CONVERTER ADC 0x4000B000 0x0 0x100 registers n ADC0 43 CR ADCn Control Register 0x20 32 read-write n 0x0 0xFF ASTOP ADC Stop 7 1 write-only START ADC conversion start 0 1 read-write CR1 ADCn Clock Control Register 0x8 32 read-write n 0x80 0xFFFF ADCPD ADC Power down 7 1 ADCPDA ADC R-ADC disable to save power 15 1 CLKDIV ADC clock divider 8 7 CLKINVT divided clock inversion 5 1 EXTCLK ADCuse external clock 6 1 CSCR ADCn Current Sequence/Channel Register 0x4 32 read-write n 0x0 0xFF CACH Current Active Channel 0 4 read-only CSEQN Current Sequence Number 4 3 DDR ADC DMA Data Register 0x2C 32 read-only n 0x0 0xFFFF ADDMAR ADC conversion result data 4 12 ADMACH ADC data channel indicator 0 4 DR0 ADC Sequence Data Register 1 0x30 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR1 ADC Sequence Data Register 2 0x34 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR2 ADC Sequence Data Register 3 0x38 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR3 ADC Sequence Data Register 4 0x3C 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR4 ADC Sequence Data Register 5 0x40 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR5 ADC Sequence Data Register 6 0x44 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR6 ADC Sequence Data Register 7 0x48 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR7 ADC Sequence Data Register 8 0x4C 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 IER Interrupt Enable Register 0x28 32 read-write n 0x0 0xFF DMAIRQE DMA done interrupt enable 4 1 EOCIRQE Conversion Complete interrupt enable 0 1 EOSIRQE ADC End of Sequence interrupt enable 2 1 TRGIRQE ADC Trigger conversion intterupt enable 3 1 MR ADCn Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADCMOD ADC convert mode 4 2 ADEN ADC Enable 7 1 ARST Stop at end of sequence 6 1 DMACH DMA Channel option 18 1 DMAEN DMA Enable 17 1 SEQCNT Sequence count 8 3 STSEL Sampling Time Selection 12 5 TRGSEL ADC Trigger source sel 0 2 SCSR ADC Sequence Channel select 0x18 32 read-write n 0x0 0xFFFFFFFF SEQ0CH 1st sequence coversion channel selection 0 4 SEQ1CH 2nd sequence coversion channel selection 4 4 SEQ2CH 3rd sequence coversion channel selection 8 4 SEQ3CH 4th sequence coversion channel selection 12 4 SEQ4CH 5th sequence coversion channel selection 16 4 SEQ5CH 6th sequence coversion channel selection 20 4 SEQ6CH 7th sequence coversion channel selection 24 4 SEQ7CH 8th sequence coversion channel selection 28 4 SR ADC Status Register 0x24 32 read-write n 0x0 0xFF ABUSY ADC conversion busy flag 6 1 read-only DMAIRQ DMA received/transfer is done 4 1 DOVRUN DMA overrun flag 5 1 read-only EOC End of Conversion Flag 7 1 read-only EOCIRQ Each conversion in sequence interrupt flag 0 1 EOSIRQ End of Sequence interrupt flag 2 1 TRGIRQ ADC Trigger interrupt flag 3 1 TRG ADC Trigger Selection Register 0xC 32 read-write n 0x0 0xFFFFFFFF SEQTRG0 Sequence Trigger 0 0 3 SEQTRG1 Sequence Trigger 1 4 3 SEQTRG2 Sequence Trigger 2 8 3 SEQTRG3 Sequence Trigger 3 12 3 SEQTRG4 Sequence Trigger 4 16 3 SEQTRG5 Sequence Trigger 5 20 3 SEQTRG6 Sequence Trigger 6 24 3 SEQTRG7 Sequence Trigger 7 28 3 AD1 12-BIT A/D CONVERTER ADC 0x4000B100 0x0 0x100 registers n ADC1 44 CR ADCn Control Register 0x20 32 read-write n 0x0 0xFF ASTOP ADC Stop 7 1 write-only START ADC conversion start 0 1 read-write CR1 ADCn Clock Control Register 0x8 32 read-write n 0x80 0xFFFF ADCPD ADC Power down 7 1 ADCPDA ADC R-ADC disable to save power 15 1 CLKDIV ADC clock divider 8 7 CLKINVT divided clock inversion 5 1 EXTCLK ADCuse external clock 6 1 CSCR ADCn Current Sequence/Channel Register 0x4 32 read-write n 0x0 0xFF CACH Current Active Channel 0 4 read-only CSEQN Current Sequence Number 4 3 DDR ADC DMA Data Register 0x2C 32 read-only n 0x0 0xFFFF ADDMAR ADC conversion result data 4 12 ADMACH ADC data channel indicator 0 4 DR0 ADC Sequence Data Register 1 0x30 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR1 ADC Sequence Data Register 2 0x34 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR2 ADC Sequence Data Register 3 0x38 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR3 ADC Sequence Data Register 4 0x3C 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR4 ADC Sequence Data Register 5 0x40 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR5 ADC Sequence Data Register 6 0x44 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR6 ADC Sequence Data Register 7 0x48 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 DR7 ADC Sequence Data Register 8 0x4C 32 read-only n 0x0 0xFFFF ADCDATA ADC Sequence Data 4 12 IER Interrupt Enable Register 0x28 32 read-write n 0x0 0xFF DMAIRQE DMA done interrupt enable 4 1 EOCIRQE Conversion Complete interrupt enable 0 1 EOSIRQE ADC End of Sequence interrupt enable 2 1 TRGIRQE ADC Trigger conversion intterupt enable 3 1 MR ADCn Mode Register 0x0 32 read-write n 0x0 0xFFFFFFFF ADCMOD ADC convert mode 4 2 ADEN ADC Enable 7 1 ARST Stop at end of sequence 6 1 DMACH DMA Channel option 18 1 DMAEN DMA Enable 17 1 SEQCNT Sequence count 8 3 STSEL Sampling Time Selection 12 5 TRGSEL ADC Trigger source sel 0 2 SCSR ADC Sequence Channel select 0x18 32 read-write n 0x0 0xFFFFFFFF SEQ0CH 1st sequence coversion channel selection 0 4 SEQ1CH 2nd sequence coversion channel selection 4 4 SEQ2CH 3rd sequence coversion channel selection 8 4 SEQ3CH 4th sequence coversion channel selection 12 4 SEQ4CH 5th sequence coversion channel selection 16 4 SEQ5CH 6th sequence coversion channel selection 20 4 SEQ6CH 7th sequence coversion channel selection 24 4 SEQ7CH 8th sequence coversion channel selection 28 4 SR ADC Status Register 0x24 32 read-write n 0x0 0xFF ABUSY ADC conversion busy flag 6 1 read-only DMAIRQ DMA received/transfer is done 4 1 DOVRUN DMA overrun flag 5 1 read-only EOC End of Conversion Flag 7 1 read-only EOCIRQ Each conversion in sequence interrupt flag 0 1 EOSIRQ End of Sequence interrupt flag 2 1 TRGIRQ ADC Trigger interrupt flag 3 1 TRG ADC Trigger Selection Register 0xC 32 read-write n 0x0 0xFFFFFFFF SEQTRG0 Sequence Trigger 0 0 3 SEQTRG1 Sequence Trigger 1 4 3 SEQTRG2 Sequence Trigger 2 8 3 SEQTRG3 Sequence Trigger 3 12 3 SEQTRG4 Sequence Trigger 4 16 3 SEQTRG5 Sequence Trigger 5 20 3 SEQTRG6 Sequence Trigger 6 24 3 SEQTRG7 Sequence Trigger 7 28 3 DC0 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000400 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC1 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000410 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC2 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000420 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC3 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000430 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC4 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000440 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC5 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000450 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC6 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000460 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only DC7 DIRECT MEMORY ACCESS CONTROLLER DMAC 0x40000470 0x0 0x10 registers n CR DMA Controller Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DIR Select Direction of Transfer 1 1 PERISEL Peripheral selection 8 4 SIZE Bus transfer size 2 2 TRANSCNT Numer of DMA transfer remained 16 12 MAR DMA Controller Memory Address register 0xC 32 read-write n 0x20000000 0xFFFFFFFF MAR Memory address 0 16 PAR DMA Controller Peripheral Address register 0x8 32 read-write n 0x0 0xFFFFFFFF PAR Periphreal address 0 16 SR DMA Controller Status register 0x4 32 read-write n 0x0 0xFF DMAEN DMA enable 0 1 read-write EOT End of transfer 7 1 read-only FM FLASH MEMORY CONTROLLER FMC 0x40000100 0x0 0x100 registers n AR Flash Memory Address Register 0xC 32 read-write n 0x0 0x1FFFF FADDR 96K 4-byte word address 0 17 BOOTCR Boot ROM Remap Clear Register 0x74 32 read-write n 0x1 0xFF BOOTROM Used to clear Boot mode at end of boot code 0 1 CFG Flash Memory Config value register 0x30 32 read-write n 0x8300 0xFFFFFFFF CRCEN Enable CRC calculation at flash read 6 1 CRCINIT Initialize CRC register 7 1 HRESPD Disable AMBA AHB signal (error response) 15 1 TMRCK PGM/ERASE Timer source 12 1 TRIM FLASH TRIM value 0 4 WAIT Wait for Flash Access 8 3 WRITEKEY Write Key (0x7858) 16 16 CR Flash Memory Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF AE All Erase 8 1 read-only ERS program mode/erase mode Enable 1 1 read-write EVER Set Erase Verify mode 14 1 read-write PBLD page buffer load 3 1 read-write PBR page buffer reset 0 1 read-write PGM PGM 2 1 read-write PMODE Pmode Enable 5 1 read-write PPGM PreProgram enable 9 1 read-write PVER Set Program Verify mode 13 1 read-write TEST TEST 16 2 read-write TIMER Program/Erase Timer enable 20 1 read-write VPPOUT Enable Charge pump VPP output 15 1 read-write WE write Enable 4 1 read-write CRC Flash Memory CRC value register 0x20 32 read-write n 0x0 0xFFFFFFFF CRC CRC16 Value 0 16 DR Flash Memory Data Register 0x10 32 read-write n 0x0 0xFFFFFFFF FDATA Flash PGM data 0 32 DRTY Flash Memory Dirty bit Register 0x18 32 read-write n 0x0 0xFFFFFFFF FDRTY Write any value,cache line fill falg will be cleared 0 32 JTAGEN JTAG Protection Control Register 0x7C 32 read-write n 0x1 0xFFFFFFFF JTAGEN JTAG enable 0 1 WRITE_KEY Write Key (0xC7) 24 8 MR Flash Memory Mode Register 0x4 32 read-write n 0x1000000 0x81C303FF ACODE Flash Mode/Trim Mode 0 8 read-write AMBAEN AMBA mode enable 22 1 read-write BOOT Boot Mode enable status 31 1 read-only FEMOD Flash Mode entry status 9 1 read-only FMOD Flash Mode status 8 1 read-only IDLE Idle mode enable status 24 1 read-only TRM Trim Mode status 16 1 read-only TRMEN Trim Mode entry status 17 1 read-only VERIFY Flash verify Mode enable status 23 1 read-write PROT Internal flash memory protection Register 0x78 32 read-write n 0x0 0xFFFFFFFF APR Enable/Remove all protection 23 1 PAS Protection Area Selection 16 3 WP0 0x0000-0x0FFF 0 1 WP1 0x1000-0x1FFF 1 1 WP10 0xA000-0xAFFF 10 1 WP11 0xB000-0xBFFF 11 1 WP12 0xC000-0xCFFF 12 1 WP13 0xD000-0xDFFF 13 1 WP14 0xE000-0xEFFF 14 1 WP15 0xF000-0xFFFF 15 1 WP2 0x2000-0x2FFF 2 1 WP3 0x3000-0x3FFF 3 1 WP4 0x4000-0x4FFF 4 1 WP5 0x5000-0x5FFF 5 1 WP6 0x6000-0x6FFF 6 1 WP7 0x7000-0x7FFF 7 1 WP8 0x8000-0x8FFF 8 1 WP9 0x9000-0x9FFF 9 1 WRITEKEY Write Key 24 8 TICK Flash Memory Tick Timer register 0x1C 32 read-write n 0x0 0xFFFFFFFF FTICK TICK 0 18 TMR Flash Memory Timer Register 0x14 32 read-write n 0x9C4 0xFFFF TMR Erase/PGM timer 0 16 FRT 32bit Free Run Timer FRT 0x40000600 0x0 0x20 registers n FRT 4 CNT Free Run Timer Counter Register 0xC 32 read-only n 0x0 0xFFFFFFFF CR Free Run Timer Control Register 0x4 32 read-write n 0x0 0xFF CNTREQ FRT Counter Read Request bitr 3 1 FCLR Counter Register Clear 2 1 FEN FRT Enable 0 1 FHOLD Counter Register Hold 1 1 MR Free Run Timer Mode Register 0x0 32 read-write n 0x0 0xFF CLKSEL FRT Counter clock source 3 2 MCD Counter Match clear Disable flag 2 1 MIE MatchInterrupt Enable 0 1 OVIE Overflow Interrupt Enable 1 1 PER Free Run Timer Period Match Register 0x8 32 read-write n 0x0 0xFFFFFFFF DATA FRT Match Data 0 32 SR Free Run Timer Status Register 0x10 32 read-write n 0x0 0xFF MIF Match Interrupt flag 0 1 OVIF Overflow Interrupt flag 1 1 RACK Read Counter Acknowledge bit 2 1 IC0 I2C Interface I2C 0x4000A000 0x0 0x100 registers n I2C0 36 CR I2C Control Register 0x14 32 read-write n 0x0 0xFF ACKEN ACK enabit bit in receiver mode 3 1 I2CEN I2C Enable Bit 6 1 IIF Interrupt Flag 7 1 INTDEL Interval delay between Addr and Data 8 2 INTEN Interrupt enable bit 4 1 SOFTRST Soft reset enable bit 5 1 START transmission start bit in master mode 0 1 STOP Stop enable bit 1 1 DR I2C Data Register 0x0 32 read-write n 0x0 0xFF DR Data 0 8 SAR I2C Slave Address Register 0xC 32 read-write n 0x0 0xFF GCEN general call enable bit 0 1 SVAD 7 bits slave address 1 7 SCLH I2C SCL HIGH duration Register 0x1C 32 read-write n 0xFFFF 0xFFFF SCLH SCL High duration value 0 16 SCLL I2C SCL LOW duration Register 0x18 32 read-write n 0xFFFF 0xFFFF SCLL SCL Low duration value 0 16 SDH SDA Hold Register 0x20 32 read-write n 0x7F 0x7FFF SDH SDA Hold time 0 15 SR SR Status register 0x8 32 read-write n 0x0 0xFFFFFFFF BUSY busy flag 2 1 GCALL General call flag 7 1 MLOST Mastership lost flag 3 1 RXACK RX ack flag 0 1 SSEL slave flag (start condition received) 4 1 STOP Stop Flag 5 1 TEND 1 byte transmission complete flag 6 1 TMODE Transmit/reciever mode flag 1 1 IC1 I2C Interface I2C 0x4000A100 0x0 0x100 registers n I2C1 37 CR I2C Control Register 0x14 32 read-write n 0x0 0xFF ACKEN ACK enabit bit in receiver mode 3 1 I2CEN I2C Enable Bit 6 1 IIF Interrupt Flag 7 1 INTDEL Interval delay between Addr and Data 8 2 INTEN Interrupt enable bit 4 1 SOFTRST Soft reset enable bit 5 1 START transmission start bit in master mode 0 1 STOP Stop enable bit 1 1 DR I2C Data Register 0x0 32 read-write n 0x0 0xFF DR Data 0 8 SAR I2C Slave Address Register 0xC 32 read-write n 0x0 0xFF GCEN general call enable bit 0 1 SVAD 7 bits slave address 1 7 SCLH I2C SCL HIGH duration Register 0x1C 32 read-write n 0xFFFF 0xFFFF SCLH SCL High duration value 0 16 SCLL I2C SCL LOW duration Register 0x18 32 read-write n 0xFFFF 0xFFFF SCLL SCL Low duration value 0 16 SDH SDA Hold Register 0x20 32 read-write n 0x7F 0x7FFF SDH SDA Hold time 0 15 SR SR Status register 0x8 32 read-write n 0x0 0xFFFFFFFF BUSY busy flag 2 1 GCALL General call flag 7 1 MLOST Mastership lost flag 3 1 RXACK RX ack flag 0 1 SSEL slave flag (start condition received) 4 1 STOP Stop Flag 5 1 TEND 1 byte transmission complete flag 6 1 TMODE Transmit/reciever mode flag 1 1 MP0 MOTOR PULSE-WIDTH-MODULATOR MPWM 0x40004000 0x0 0x1000 registers n MPWM0 24 MPWM0PROT 25 MPWM0OVV 26 ATR1 MPWMn ADC Trigger Counter 1 Register 0x58 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR2 MPWMn ADC Trigger Counter 2 Register 0x5C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR3 MPWMn ADC Trigger Counter 3 Register 0x60 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR4 MPWMn ADC Trigger Counter 4 Register 0x64 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR5 MPWMn ADC Trigger Counter 5 Register 0x68 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR6 MPWMn ADC Trigger Counter 6 Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 CNT MPWM Counter Register 0x38 32 read-write n 0x0 0xFFFF CNT pwm counter value 0 16 CR1 MPWM Control Register 1 0x28 32 read-write n 0x0 0xFFFF IRQN IRQ interval Number 8 3 PWMEN PWM enable 0 1 CR2 MPWM Control Register 2 0x2C 32 read-write n 0x0 0xFF HALT PWM HALT 7 1 PSTART PWM start 0 1 DTR MPWM Dead Time Register 0x3C 32 read-write n 0x0 0xFFFF DT dead time value 0 8 DTCLK dead time clk select 8 1 DTEN dead time Enable 15 1 PSHRT Protect Short condition 14 1 DUH MPWM Duty UH Register 0x10 32 read-write n 0x1 0xFFFF DUTY duty of UH output 0 16 DUL MPWM Duty UL Register 0x1C 32 read-write n 0x1 0xFFFF DUTY duty of UL output 0 16 DVH MPWM Duty VH Register 0x14 32 read-write n 0x1 0xFFFF DUTY duty of VH data 0 16 DVL MPWM Duty UL Register 0x20 32 read-write n 0x1 0xFFFF DUTY duty of VL output 0 16 DWH MPWM Duty WH Register 0x18 32 read-write n 0x1 0xFFFF DUTY duty of WH output 0 16 DWL MPWM Duty WL Register 0x24 32 read-write n 0x1 0xFFFF DUTY duty of WL output 0 16 FOR MPWM Forced Output Control Register 0x8 32 read-write n 0x0 0xFF UHFL U High Forced Level 3 1 ULFL U Low Forced Level 0 1 VHFL V High Forced Level 4 1 VLFL V Low Forced Level 1 1 WHFL W High Forced Level 5 1 WLFL W Low Forced Level 2 1 IER MPWM Interrupt Enable Register 0x34 32 read-write n 0x0 0xFF BOTIE bottom interrupt enable 6 1 DUH_ATR4IEN duty UH/ATR4 interrupt enable 3 1 DUL_ATR1IEN duty UL/ATR1 interrupt enable 0 1 DVH_ATR5IEN duty VL/ATR5 interrupt enable 4 1 DVL_ATR2IEN duty VL/ATR2 interrupt enable 1 1 DWH_ATR6IEN duty WH/ATR6 interrupt enable 5 1 DWL_ATR3IEN duty WL/ATR3 interrupt enable 2 1 PRDIEN Period interrupt enable 7 1 MR MPWM Mode Register 0x0 32 read-write n 0x0 0xFFFF BUP period duty update at Bottom match 4 1 MCHMOD Motor control channel mode 1 2 MOTORB Motor Bit 15 1 TUP period, duty values updated at period match 5 1 UAO Update timing 7 1 UPDOWN PWM counter mode 0 1 OLR MPWM Output Level Register 0x4 32 read-write n 0x0 0xFF UHL U High Level 3 1 ULL U Low Level 0 1 VHL V High Level 4 1 VLL V Low Level 1 1 WHL W High level 5 1 WLL W Low Level 2 1 PCR0 MPWM Protection control Register (PRTIN pin) 0x40 32 read-write n 0x0 0xFFFF PROTD Input 0 Debounce 8 3 PROTIE Protection Interrupt Enable 7 1 PROTOEN Enable Protection Input 0 pin 15 1 PROTPOL Input 0 Polarity 14 1 UHPROTM UH protection output 3 1 ULPROTM UL protection output 0 1 VHPROTM VH protection output 4 1 VLPROTM VL protection output 1 1 WHPROTM WH protection output 5 1 WLPROTM WL protection output 2 1 PCR1 MPWM Protection control Register (OVIN pin) 0x48 32 read-write n 0x0 0xFFFF PROTD Input 0 Debounce 8 3 PROTIE Protection Interrupt Enable 7 1 PROTOEN Enable Protection Input 0 pin 15 1 PROTPOL Input 0 Polarity 14 1 UHPROT UH protection output 3 1 ULPROT UL protection output 0 1 VHPROT VH protection output 4 1 VLPROT VL protection output 1 1 WHPROT WH protection output 5 1 WLPROT WL protection output 2 1 PRD MPWM Period Register 0xC 32 read-write n 0x2 0xFFFF PERIOD PWM period 0 16 PSR0 MPWM Protection Status Register (PRTIN pin) 0x44 32 read-write n 0x0 0xFFFFFFFF PROTIF Protection Interrupt status 7 1 PROTKEY lock safety pattern to set or reset protection 8 8 UHPROTF UH Protection Flag status 3 1 ULPROTF UL Protection Flag status 0 1 VHPROTF VH Protection Flag status 4 1 VLPROTF VL Protection Flag status 1 1 WHPROTF WH Protection Flag status 5 1 WLPROTF WL Protection Flag status 2 1 PSR1 MPWM Protection Status Register (OVIN pin) 0x4C 32 read-write n 0x0 0xFFFFFFFF PROTIF Protection Interrupt status 7 1 PROTKEY lock safety pattern to set or reset protection 8 8 UHPROTF UH Protection Flag status 3 1 ULPROTF UL Protection Flag status 0 1 VHPROTF VH Protection Flag status 4 1 VLPROTF VL Protection Flag status 1 1 WHPROTF WH Protection Flag status 5 1 WLPROTF WL Protection Flag status 2 1 SR MPWM Status Register 0x30 32 read-write n 0x0 0xFFFF BOTIF PWM bottom interrupt flag 6 1 DOWN PWM count up/down 15 1 DUH_ATR4IF duty UH/ATR4 interrupt flag 3 1 DUL_ATR1IF duty UL/ATR1 interrupt flag 0 1 DVH_ATR5IF duty VH/ATR5 interrupt flag 4 1 DVL_ATR2IF duty VL/ATR2 interrupt flag 1 1 DWH_ATR6IF duty WH/ATR6 interrupt flag 5 1 DWL_ATR3IF duty WL/ATR3 interrupt flag 2 1 IRQCNT PWM count number of period match 12 3 PRDIF PWM period interrupt flag 7 1 MP1 MOTOR PULSE-WIDTH-MODULATOR MPWM 0x40005000 0x0 0x1000 registers n MPWM1 27 MPWM1PROT 28 MPWM1OVV 29 ATR1 MPWMn ADC Trigger Counter 1 Register 0x58 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR2 MPWMn ADC Trigger Counter 2 Register 0x5C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR3 MPWMn ADC Trigger Counter 3 Register 0x60 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR4 MPWMn ADC Trigger Counter 4 Register 0x64 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR5 MPWMn ADC Trigger Counter 5 Register 0x68 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 ATR6 MPWMn ADC Trigger Counter 6 Register 0x6C 32 read-write n 0x0 0xFFFFFFFF ATCNT ADC Trigger counter 0 16 ATMOD ADC Trigger mode register 16 2 ATUDT Trigger register update mode 19 1 CNT MPWM Counter Register 0x38 32 read-write n 0x0 0xFFFF CNT pwm counter value 0 16 CR1 MPWM Control Register 1 0x28 32 read-write n 0x0 0xFFFF IRQN IRQ interval Number 8 3 PWMEN PWM enable 0 1 CR2 MPWM Control Register 2 0x2C 32 read-write n 0x0 0xFF HALT PWM HALT 7 1 PSTART PWM start 0 1 DTR MPWM Dead Time Register 0x3C 32 read-write n 0x0 0xFFFF DT dead time value 0 8 DTCLK dead time clk select 8 1 DTEN dead time Enable 15 1 PSHRT Protect Short condition 14 1 DUH MPWM Duty UH Register 0x10 32 read-write n 0x1 0xFFFF DUTY duty of UH output 0 16 DUL MPWM Duty UL Register 0x1C 32 read-write n 0x1 0xFFFF DUTY duty of UL output 0 16 DVH MPWM Duty VH Register 0x14 32 read-write n 0x1 0xFFFF DUTY duty of VH data 0 16 DVL MPWM Duty UL Register 0x20 32 read-write n 0x1 0xFFFF DUTY duty of VL output 0 16 DWH MPWM Duty WH Register 0x18 32 read-write n 0x1 0xFFFF DUTY duty of WH output 0 16 DWL MPWM Duty WL Register 0x24 32 read-write n 0x1 0xFFFF DUTY duty of WL output 0 16 FOR MPWM Forced Output Control Register 0x8 32 read-write n 0x0 0xFF UHFL U High Forced Level 3 1 ULFL U Low Forced Level 0 1 VHFL V High Forced Level 4 1 VLFL V Low Forced Level 1 1 WHFL W High Forced Level 5 1 WLFL W Low Forced Level 2 1 IER MPWM Interrupt Enable Register 0x34 32 read-write n 0x0 0xFF BOTIE bottom interrupt enable 6 1 DUH_ATR4IEN duty UH/ATR4 interrupt enable 3 1 DUL_ATR1IEN duty UL/ATR1 interrupt enable 0 1 DVH_ATR5IEN duty VL/ATR5 interrupt enable 4 1 DVL_ATR2IEN duty VL/ATR2 interrupt enable 1 1 DWH_ATR6IEN duty WH/ATR6 interrupt enable 5 1 DWL_ATR3IEN duty WL/ATR3 interrupt enable 2 1 PRDIEN Period interrupt enable 7 1 MR MPWM Mode Register 0x0 32 read-write n 0x0 0xFFFF BUP period duty update at Bottom match 4 1 MCHMOD Motor control channel mode 1 2 MOTORB Motor Bit 15 1 TUP period, duty values updated at period match 5 1 UAO Update timing 7 1 UPDOWN PWM counter mode 0 1 OLR MPWM Output Level Register 0x4 32 read-write n 0x0 0xFF UHL U High Level 3 1 ULL U Low Level 0 1 VHL V High Level 4 1 VLL V Low Level 1 1 WHL W High level 5 1 WLL W Low Level 2 1 PCR0 MPWM Protection control Register (PRTIN pin) 0x40 32 read-write n 0x0 0xFFFF PROTD Input 0 Debounce 8 3 PROTIE Protection Interrupt Enable 7 1 PROTOEN Enable Protection Input 0 pin 15 1 PROTPOL Input 0 Polarity 14 1 UHPROTM UH protection output 3 1 ULPROTM UL protection output 0 1 VHPROTM VH protection output 4 1 VLPROTM VL protection output 1 1 WHPROTM WH protection output 5 1 WLPROTM WL protection output 2 1 PCR1 MPWM Protection control Register (OVIN pin) 0x48 32 read-write n 0x0 0xFFFF PROTD Input 0 Debounce 8 3 PROTIE Protection Interrupt Enable 7 1 PROTOEN Enable Protection Input 0 pin 15 1 PROTPOL Input 0 Polarity 14 1 UHPROT UH protection output 3 1 ULPROT UL protection output 0 1 VHPROT VH protection output 4 1 VLPROT VL protection output 1 1 WHPROT WH protection output 5 1 WLPROT WL protection output 2 1 PRD MPWM Period Register 0xC 32 read-write n 0x2 0xFFFF PERIOD PWM period 0 16 PSR0 MPWM Protection Status Register (PRTIN pin) 0x44 32 read-write n 0x0 0xFFFFFFFF PROTIF Protection Interrupt status 7 1 PROTKEY lock safety pattern to set or reset protection 8 8 UHPROTF UH Protection Flag status 3 1 ULPROTF UL Protection Flag status 0 1 VHPROTF VH Protection Flag status 4 1 VLPROTF VL Protection Flag status 1 1 WHPROTF WH Protection Flag status 5 1 WLPROTF WL Protection Flag status 2 1 PSR1 MPWM Protection Status Register (OVIN pin) 0x4C 32 read-write n 0x0 0xFFFFFFFF PROTIF Protection Interrupt status 7 1 PROTKEY lock safety pattern to set or reset protection 8 8 UHPROTF UH Protection Flag status 3 1 ULPROTF UL Protection Flag status 0 1 VHPROTF VH Protection Flag status 4 1 VLPROTF VL Protection Flag status 1 1 WHPROTF WH Protection Flag status 5 1 WLPROTF WL Protection Flag status 2 1 SR MPWM Status Register 0x30 32 read-write n 0x0 0xFFFF BOTIF PWM bottom interrupt flag 6 1 DOWN PWM count up/down 15 1 DUH_ATR4IF duty UH/ATR4 interrupt flag 3 1 DUL_ATR1IF duty UL/ATR1 interrupt flag 0 1 DVH_ATR5IF duty VH/ATR5 interrupt flag 4 1 DVL_ATR2IF duty VL/ATR2 interrupt flag 1 1 DWH_ATR6IF duty WH/ATR6 interrupt flag 5 1 DWL_ATR3IF duty WL/ATR3 interrupt flag 2 1 IRQCNT PWM count number of period match 12 3 PRDIF PWM period interrupt flag 7 1 PA GENERAL PURPOSE I/O GPIO 0x40002000 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 write-only n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PB GENERAL PURPOSE I/O GPIO 0x40002100 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 write-only n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PC GENERAL PURPOSE I/O GPIO 0x40002200 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 write-only n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PCA PORT CONTROL UNIT PCU 0x40001000 0x0 0x100 registers n GPIOAE 16 GPIOAO 17 CR PORT n Pin Control Register 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCB PORT CONTROL UNIT PCU 0x40001100 0x0 0x100 registers n GPIOBE 18 GPIOBO 19 CR PORT n Pin Control Register 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCC PORT CONTROL UNIT PCU 0x40001200 0x0 0x100 registers n GPIOCE 20 GPIOCO 21 CR PORT n Pin Control Register 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCD PORT CONTROL UNIT PCU 0x40001300 0x0 0x100 registers n GPIODE 22 GPIODO 23 CR PORT n Pin Control Register 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCE PORT CONTROL UNIT PCU 0x40001400 0x0 0x100 registers n GPIOEE 50 GPIOEO 51 CR PORT n Pin Control Register 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PCF PORT CONTROL UNIT PCU 0x40001500 0x0 0x100 registers n GPIOFE 52 GPIOFO 53 CR PORT n Pin Control Register 0x4 32 read-write n 0xFFFFFFFF 0xFFFFFFFF P0 P0 control SEL 0 2 P1 P1 control select 2 2 P10 P10 control SEL 20 2 P11 P11 control select 22 2 P12 P12 control SEL 24 2 P13 P13 control select 26 2 P14 P14 control SEL 28 2 P15 P15 control select 30 2 P2 P2 control SEL 4 2 P3 P3 control select 6 2 P4 P4 control SEL 8 2 P5 P5 control select 10 2 P6 P6 control SEL 12 2 P7 P7 control select 14 2 P8 P8 control SEL 16 2 P9 P9 control select 18 2 DER PORT n Debounce Enable Register 0xC 32 read-write n 0x0 0xFFFF P0 P0 Debounce enable 0 1 P1 P1 Debounce enable 1 1 P10 P10 Debounce enable 10 1 P11 P11 Debounce enable 11 1 P12 P12 Debounce enable 12 1 P13 P13 Debounce enable 13 1 P14 P14 Debounce enable 14 1 P15 P15 Debounce enable 15 1 P2 P2 Debounce enable 2 1 P3 P3 Debounce enable 3 1 P4 P4 Debounce enable 4 1 P5 P5 Debounce enable 5 1 P6 P6 Debounce enable 6 1 P7 P7 Debounce enable 7 1 P8 P8 Debounce enable 8 1 P9 P9 Debounce enable 9 1 ICR PORT n Interrupt Control Register 0x18 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt control 0 2 P1 P1 interrupt control 2 2 P10 P10 interrupt control 20 2 P11 P11 interrupt control 22 2 P12 P12 interrupt control 24 2 P13 P13 interrupt control 26 2 P14 P14 interrupt control 28 2 P15 P15 interrupt control 30 2 P2 P2 interrupt control 4 2 P3 P3 interrupt control 6 2 P4 P4 interrupt control 8 2 P5 P5 interrupt control 10 2 P6 P6 interrupt control 12 2 P7 P7 interrupt control 14 2 P8 P8 interrupt control 16 2 P9 P9 interrupt control 18 2 IER PORT n Interrupt Enable Register 0x10 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt enable 0 2 P1 P1 interrupt select 2 2 P10 P10 interrupt SEL 20 2 P11 P11 interrupt select 22 2 P12 P12 interrupt SEL 24 2 P13 P13 interrupt select 26 2 P14 P14 interrupt SEL 28 2 P15 P15 interrupt select 30 2 P2 P2 interrupt SEL 4 2 P3 P3 interrupt select 6 2 P4 P4 interrupt SEL 8 2 P5 P5 interrupt select 10 2 P6 P6 interrupt SEL 12 2 P7 P7 interrupt select 14 2 P8 P8 interrupt SEL 16 2 P9 P9 interrupt select 18 2 ISR PORT n Interrupt Status Register 0x14 32 read-write n 0x0 0xFFFFFFFF P0 P0 interrupt status 0 2 P1 P1 interrupt status 2 2 P10 P10 interrupt status 20 2 P11 P11 interrupt status 22 2 P12 P12 interrupt status 24 2 P13 P13 interrupt status 26 2 P14 P14 interrupt status 28 2 P15 P15 interrupt status 30 2 P2 P2 interrupt status 4 2 P3 P3 interrupt status 6 2 P4 P4 interrupt status 8 2 P5 P5 interrupt status 10 2 P6 P6 interrupt status 12 2 P7 P7 interrupt status 14 2 P8 P8 interrupt status 16 2 P9 P9 interrupt status 18 2 MR PORT n Pin MUX Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 P0 MUX SEL 0 2 P1 P1 Pin Mux select 2 2 P10 P10 MUX SEL 20 2 P11 P11 Pin Mux select 22 2 P12 P12 MUX SEL 24 2 P13 P13 Pin Mux select 26 2 P14 P14 MUX SEL 28 2 P15 P15 Pin Mux select 30 2 P2 P2 MUX SEL 4 2 P3 P3 Pin Mux select 6 2 P4 P4 MUX SEL 8 2 P5 P5 Pin Mux select 10 2 P6 P6 MUX SEL 12 2 P7 P7 Pin Mux select 14 2 P8 P8 MUX SEL 16 2 P9 P9 Pin Mux select 18 2 PCR PORT n Pull-up Resistor Control Register 0x8 32 read-write n 0x0 0xFFFF P0 P0 pull-up enable 0 1 P1 P1 pull-up enable 1 1 P10 P10 pull-up enable 10 1 P11 P11 pull-up enable 11 1 P12 P12 pull-up enable 12 1 P13 P13 pull-up enable 13 1 P14 P14 pull-up enable 14 1 P15 P15 pull-up enable 15 1 P2 P2 pull-up enable 2 1 P3 P3 pull-up enable 3 1 P4 P4 pull-up enable 4 1 P5 P5 pull-up enable 5 1 P6 P6 pull-up enable 6 1 P7 P7 pull-up enable 7 1 P8 P8 pull-up enable 8 1 P9 P9 pull-up enable 9 1 PD GENERAL PURPOSE I/O GPIO 0x40002300 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 write-only n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PE GENERAL PURPOSE I/O GPIO 0x40002400 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 write-only n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PF GENERAL PURPOSE I/O GPIO 0x40002500 0x0 0x100 registers n BCR PORT n Bit Clear Register 0xC 32 write-only n 0x0 0xFFFF P0 P0 bit clear 0 1 P1 P1 bit clear 1 1 P10 P10 bit clear 10 1 P11 P11 bit clear 11 1 P12 P12 bit clear 12 1 P13 P13 bit clear 13 1 P14 P14 bit clear 14 1 P15 P15 bit clear 15 1 P2 P2 bit clear 2 1 P3 P3 bit clear 3 1 P4 P4 bit clear 4 1 P5 P5 bit clear 5 1 P6 P6 bit clear 6 1 P7 P7 bit clear 7 1 P8 P8 bit clear 8 1 P9 P9 bit clear 9 1 BSR PORT n Bit Set Register 0x8 32 write-only n 0x0 0xFFFF P0 P0 bit set 0 1 P1 P1 bit set 1 1 P10 P10 bit set 10 1 P11 P11 bit set 11 1 P12 P12 bit set 12 1 P13 P13 bit set 13 1 P14 P14 bit set 14 1 P15 P15 bit set 15 1 P2 P2 bit set 2 1 P3 P3 bit set 3 1 P4 P4 bit set 4 1 P5 P5 bit set 5 1 P6 P6 bit set 6 1 P7 P7 bit set 7 1 P8 P8 bit set 8 1 P9 P9 bit set 9 1 IDR PORT n Input Data Register 0x4 32 read-only n 0x0 0xFFFF P0 P0 Input level 0 1 P1 P1 Input level 1 1 P10 P10 Input level 10 1 P11 P11 Input level 11 1 P12 P12 Input level 12 1 P13 P13 Input level 13 1 P14 P14 Input level 14 1 P15 P15 Input level 15 1 P2 P2 Input level 2 1 P3 P3 Input level 3 1 P4 P4 Input level 4 1 P5 P5 Input level 5 1 P6 P6 Input level 6 1 P7 P7 Input level 7 1 P8 P8 Input level 8 1 P9 P9 Input level 9 1 ODR PORT n Output Data Register 0x0 32 read-write n 0x0 0xFFFF P0 P0 Output level 0 1 P1 P1 Output level 1 1 P10 P10 Output level 10 1 P11 P11 Output level 11 1 P12 P12 Output level 12 1 P13 P13 Output level 13 1 P14 P14 Output level 14 1 P15 P15 Output level 15 1 P2 P2 Output level 2 1 P3 P3 Output level 3 1 P4 P4 Output level 4 1 P5 P5 Output level 5 1 P6 P6 Output level 6 1 P7 P7 Output level 7 1 P8 P8 Output level 8 1 P9 P9 Output level 9 1 PORTEN Port Access Eable PORTEN 0x40001FF0 0x0 0x10 registers n EN Port Access Enable 0x0 32 read-write n 0x0 0xFFFF SCU SYSTEM CONTROL UNIT SCU 0x40000000 0x0 0x100 registers n LVDDETECT 0 SYSCLKFAIL 1 XOSCFAIL 2 CIDR Chip ID Register 0x0 32 read-only n 0xAC330384 0xFFFFFFFF CIDR2 Revision ID Register 0xC 32 read-only n 0x2 0xFFFFFFFF CMR Clock Monitoring Register 0x48 32 read-write n 0x111 0x8FFF EOSCFAIL external OSC failed flag 1 1 read-write EOSCIE external OSC failed interrupt enable 2 1 read-write EOSCMNT Externaler OSC monitor enable 3 1 read-write EOSCSTS external OSC status 0 1 read-write MCLKFAIL MCLK Failed flag 5 1 read-write MCLKIE MCLK fail Interrupt enable 6 1 read-write MCLKMNT MCLK monitor enable 7 1 read-write MCLKREC MCLK failed auto recovery 15 1 read-only MCLKSTS MCLK clock status 4 1 read-write SX0SCFAIL Sub Oscillator Fail Interrupt 9 1 read-write SX0SCIE Sub Oscillator Fail Interrupt Enable 10 1 read-write SX0SCMNT Sub Oscillator Monitoring Enable 11 1 read-write SX0SCSTS Sub Oscillator clock status 8 1 read-write COR Clock Output Register 0x50 32 read-write n 0xF 0xFF CLKODIV clock output divider value 0 4 read-write CLKOEN clock output enable 4 1 read-write CSCR Clock Source Control Register 0x40 32 read-write n 0x20 0xFF EOSCON External crystal OSC control 0 2 IOSCCON Internal OSC control 2 2 RINGOSCCON Internal ring OSC control 4 2 SXOSCEN External Sub Oscillator Enable 7 1 DBCLK1 PA and PB Debounce Clock Control Register 0x9C 32 read-write n 0x10001 0xFFFFFFFF PADCSEL debouce clock for port A source clock sel 8 3 PADDIV PORT A debounce divider 0 8 PBDDIV PORT B debounce divider 16 8 PBDSEL debouce clock for port B source clock sel 24 3 DBCLK2 PC and PD Debounce Control Register 0xA0 32 read-write n 0x10001 0xFFFFFFFF PCDCSEL debouce clock for port C source clock sel 8 3 PCDDIV PORT C debounce divider 0 8 PDDCSEL debouce clock for port D source clock sel 24 3 PDDDIV PORT D debounce divider 16 8 DBCLK3 PE and PF Debounce Clock Control 0xA4 32 read-write n 0x10001 0xFFFFFFFF PEDCSEL Debouce clock for PORT E source select bit 8 3 PEDDIV PORT E Debounce clock divider 0 8 PFDCSEL Debounce Clock for PORT F source select bitl 24 3 PFDDIV PORT F Clock N divider 16 8 EMODR External Mode Status Register 0x84 32 read-only n 0x0 0xFF BOOT boot pin level 0 1 SCANMD scan mode pin level 2 1 TEST TEST PIN level 1 1 EOSCR External Oscillator Control Register 0x80 32 read-write n 0x2 0xFFFF ISEL select current 8 2 read-write ISELEN write enable for bit field ISEL 15 1 write-only NCEN write enable for Noise Canceling delay 7 1 write-only NCSEL Select Noise Canceling delay 0 2 read-write IOSCTRIM Internal OSC Trim Register 0x6C 32 read-write n 0x0 0x87BF9F LT interal oscillator LT trim value 10 4 LTEN LTEN 15 1 LTM interal oscillator LT trim value 8 2 TSL TSL 16 3 TSLEN TSLEN 23 1 UDCEN UDCEN 7 1 UDCH UDCH 3 2 UDCL UDCL 0 3 LVDCON Brown out detect Control Register 0x68 32 read-write n 0x1 0xFFFFFF BODEN Brown out detection Enable 0 1 read-write BODLVL BODLVL 1 1 read-only BODSEL Brown Out Level Select 8 2 read-write BODTE BODTE 23 1 write-only BODTRIM BODTRIM 16 2 read-write SELEN SELEN 15 1 read-write MCCR1 Trace and SysTick Clock Control Register 0x90 32 read-write n 0x4040001 0xFFFFFFFF STCSEL systick clock source sel 8 3 read-write STDIV systick divider 0 8 read-write TRACEDIV TRACEDIV 16 8 read-write TRCPOL TRCPOL 31 1 write-only TRCSEL trace clock source sel 24 3 read-write MCCR2 MPWM0 and MPWM1 Clock Control Register 0x94 32 read-write n 0x0 0xFFFFFFFF PWM0CSEL pwm0 clock sel 8 3 PWM0DIV PWM0 divider 0 8 PWM1CSEL PWM1 clock sel 24 3 PWM1DIV pwm1 divider 16 8 MCCR3 TEXT0 and WDT clock control registers 0x98 32 read-write n 0x10001 0xFFFFFFFF TEXT0CSEL timer ext0 clock sel 24 3 TEXT0DIV timer ext0 divider 16 8 WDTCSEL WDT clock sel 8 3 WDTDIV WDT divider 0 8 MCCR4 Alternative ADC and NMI Debounce Clock control 0xA8 32 read-write n 0x1 0xFFFFFFFF ADCCDIV ADC Clock N divider 16 8 ADCCSEL ADC clock source select 24 3 NMICSEL Debouce clock for NMI source select bit 8 3 NMIDDIV NMI Debounce clock divider 0 8 NMIR NMI Control Register 0x4C 32 read-write n 0xA0080 0xFFFFFFFF BODEN Brown Out Dectect NMI Enable 0 1 read-write BODSTS Brown Out Detect Status 8 1 read-only MCLKFAILEN MCLK Fail NMI Enable 1 1 read-write MCLKFAILSTS MCLK Fail Status 9 1 read-only NMIINT NMI Interrupt state 18 1 read-write NMIINTSTS NMI Interrupt Status 15 1 read-only NMIPINDBEN NMI Pin Debounce status 17 1 read-write NMIPINEN NMI Pin Enable 7 1 read-write NMIPINSTS NMI Pin status 19 1 read-only OVP0EN Over Voltage Protection NMI Enable 3 1 read-write OVP0STS Over Voltage Protection Status 11 1 read-only OVP1EN Over Voltage Protection NMI Enable 5 1 read-write OVP1STS Over Voltage Protection Status 13 1 read-only PROT0EN Protection Condition NMI Enable 4 1 read-write PROT0STS Protection condition status 12 1 read-only PROT1EN Protection Condition NMI Enable 6 1 read-write PROT1STS Protection condition status 14 1 read-only WDTINTEN WDT interrupt for NMI Enable 2 1 read-write WDTINTSTS Watch Dog status 10 1 read-only PCER1 Peripheral Clock Enable Register 1 0x30 32 read-write n 0xF 0x3FFFFFF DMA DMA Function Enable 4 1 FRT FRT Enable 7 1 GPIOA GPIOA 8 1 GPIOB GPIOB 9 1 GPIOC GPIOC 10 1 GPIOD GPIOD 11 1 GPIOE GPIOE 12 1 GPIOF GPIOF 13 1 TIMER0 TIMER0 16 1 TIMER1 TIMER1 17 1 TIMER2 TIMER2 18 1 TIMER3 TIMER3 19 1 TIMER4 TIMER5 Enable 20 1 TIMER5 TIMER5 Enable 21 1 TIMER6 TIMER6 Enable 22 1 TIMER7 TIMER7 Enable 23 1 TIMER8 TIMER8 Enable 24 1 TIMER9 TIMER9 Enable 25 1 PCER2 Peripheral Clock Enable Register 2 0x34 32 read-write n 0x101 0xFFFFFF ADC0 ADC0 20 1 ADC1 ADC1 21 1 I2C0 I2C0 Enable 4 1 I2C1 I2C1 Enable 5 1 MPWM0 MPWM0 Enable 16 1 MPWM1 MPWM1 Enable 17 1 SPI0 SPI0 Enable 0 1 SPI1 SPI1 Enable 1 1 UART0 UART0 Enable 8 1 UART1 UART1 Enable 9 1 UART2 UART2 Enable 10 1 UART3 UART3 Enable 11 1 PER1 Peripheral Enable Register 1 0x28 32 read-write n 0xF 0xFFFFFFFF DMA DMA Function Enable 4 1 FRT FRT 7 1 GPIOA GPIOA 8 1 GPIOB GPIOB 9 1 GPIOC GPIOC 10 1 GPIOD GPIOD 11 1 GPIOE GPIOE 12 1 GPIOF GPIOF 13 1 TIMER0 TIMER0 16 1 TIMER1 TIMER1 17 1 TIMER2 TIMER2 18 1 TIMER3 TIMER3 19 1 TIMER4 TIMER4 Enable 20 1 TIMER5 TIMER5 Enable 21 1 TIMER6 TIMER6 Enable 22 1 TIMER7 TIMER7 Enable 23 1 TIMER8 TIMER8 Enable 24 1 TIMER9 TIMER9 Enable 25 1 PER2 Peripheral Enable Register 2 0x2C 32 read-write n 0x101 0xFFFFFF ADC0 ADC0 20 1 ADC1 ADC1 21 1 I2C0 I2C0 Enable 4 1 I2C1 I2C1 Enable 5 1 MPWM0 MPWM0 Enable 16 1 MPWM1 MPWM1 Enable 17 1 SPI0 SPI0 Enable 0 1 SPI1 SPI1 Enable 1 1 UART0 UART0 Enable 8 1 UART1 UART1 Enable 9 1 UART2 UART2 Enable 10 1 UART3 UART3 Enable 11 1 PLLCON PLL Control Register 0x60 32 read-write n 0x0 0xF1FF BYPASS FIN Bypass to FOUT 13 1 read-write FBCTRL Feedback control 4 4 read-write LOCK PLL Lock state 12 1 read-only PLLEN PLL Enable 14 1 read-write PLLRSTB PLL reset 15 1 read-write POSTDIV post divider 0 4 read-write PREDIV FIN pre divider 8 1 read-write PRER1 Peripheral Reset Enable Register 1 0x20 32 read-write n 0x3FF3F9F 0x3FF3F9F DMA DMA Reset 4 1 FMC Flash Memory controll Reset 1 1 FRT FRT Reset 7 1 GPIOA GPIOA Reset 8 1 GPIOB GPIOB Reset 9 1 GPIOC GPIOC Reset 10 1 GPIOD GPIOD Reset 11 1 GPIOE GPIOE Reset 12 1 GPIOF GPIOF Reset 13 1 PCU Port controll Reset 3 1 SCU Power Management Unit Reset 0 1 TIMER0 TIMER0 Reset 16 1 TIMER1 TIMER1 Reset 17 1 TIMER2 TIMER2 Reset 18 1 TIMER3 TIMER3 Reset 19 1 TIMER4 TIMER4 Reset 20 1 TIMER5 TIMER5 Reset 21 1 TIMER6 TIMER6 Reset 22 1 TIMER7 TIMER7 Reset 23 1 TIMER8 TIMER8 Reset 24 1 TIMER9 TIMER9 Reset 25 1 WDT Watch Dog Timer Reset 2 1 PRER2 Peripheral Reset Enable Register 2 0x24 32 read-write n 0xB30F33 0xB30F33 ADC0 ADC0 Reset 20 1 ADC1 ADC1 Reset 21 1 IIC0 IIC0 Reset 4 1 IIC1 IIC1 Reset 5 1 MPWM0 MPWM0 Reset 16 1 MPWM1 MPWM1 Reset 17 1 SPI0 SPI0 Reset 0 1 SPI1 SPI1 Reset 1 1 UART0 UART0 Reset 8 1 UART1 UART1 9 1 UART2 UART2 10 1 UART3 UART3 11 1 RSER Reset Source Enable Register 0x18 32 read-write n 0x49 0xFF CPURST CPU request reset enable 5 1 LVDRST LVD reset enable 0 1 MCKFRST MCLK failed reset enable 2 1 PINRST external pin reset enable 6 1 SWRST software reset enable 4 1 WDTRST watch dog reset enable 3 1 XFRST external OSC clock failed enable 1 1 RSSR Reset Source Status Register 0x1C 32 read-write n 0x80 0xFF CPURST cpu request reset status 5 1 LVDRST lvd reset status 0 1 MCKFRST MCLK failed reset status 2 1 PINRST extenral pin reset status 6 1 PORST power on reset status 7 1 SWRST software reset status 4 1 WDTRST watchdog timer reset status 3 1 XFRST clock failed reset status 1 1 SCCR System Clock Control Register 0x44 32 read-write n 0x0 0x7 FINSEL PLL Input source FIN Select 2 1 MCLKSEL System clock select 0 2 SMR System Mode Register 0x4 32 read-write n 0x0 0x130 PREVMODE PREVMODE 4 2 VDCAON VDCAON 8 1 SRCR System Reset Control Register 0x8 32 read-write n 0x0 0x11 STBYOP STBOP pin output polarity select bit 4 1 SWRST Internal soft reset activation 0 1 write-only VDCCON VDC Control Register 0x64 32 read-write n 0xF 0x878F01FF BMRTE BMRTE 31 1 write-only BMRTRIM BMRTRIM 24 3 read-write VDCDE VDCDE 8 1 write-only VDCTE VDC Trim Write Enable 23 1 write-only VDCTRIM VDCTRIM 16 4 read-write VDCWDLY VDC warm up delay count 0 8 read-write WUER Wakeup Source Enable Register 0x10 32 read-write n 0x0 0xFFFF FRTWUE FRTWUE 2 1 GPIOAWUE GPIOAWUE 8 1 GPIOBWUE GPIOBWUE 9 1 GPIOCWUE GPIOCWUE 10 1 GPIODWUE GPIODWUE 11 1 GPIOEWUE GPIOEWUE 12 1 GPIOFWUE GPIOFWUE 13 1 LVDWUE LVDWUE 0 1 WDTWUE WDTWUE 1 1 WUSR Wakeup Source Status Register 0x14 32 read-only n 0x0 0xFFFF FRTWU FRTWU 2 1 GPIOAWU GPIOAWU 8 1 GPIOBWU GPIOBWU 9 1 GPIOCWU GPIOCWU 10 1 GPIODWU GPIODWU 11 1 GPIOEWU GPIOEWU 12 1 GPIOFWU GPIOFWU 13 1 LVDDWU LVDWU 0 1 WDTWU WDTWU 1 1 SP0 SERIAL PERIPHERAL INTERFACE SPI 0x40009000 0x0 0x100 registers n SPI0 32 BR SPI n Baud Rate Register 0xC 32 read-write n 0xFF 0xFFFF BR buadrate 0 16 CR SPI n Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF BITSZ Transmit/receive Data bits select bit 0 2 CPHA SPI clock phase bit 3 1 CPOL SPI clock polarity bit 2 1 DRXIE DMA Rx Deone Interrupt enable bit 17 1 DTXIE DMA TX Done Interrupt enable bit 18 1 LBE Loop-back mode select bit in master mode 11 1 MS master/slaver select bit 5 1 MSBF MSB/LSB transmit select bit 4 1 RXBC Recieve buffer clear enable 19 1 RXIE Receive interrupt enable bit 14 1 SSCIE SSn Edge Chagne Interrupt enable bit 16 1 SSMASK SS Signal masking bit in slave mode 10 1 SSMO SS output signal select bit 9 1 SSMOD SS Auto/Manual Output select bit 13 1 SSOUT SS output signal select bit 12 1 SSPOL SS Signal polarity select bit 8 1 TXBC TX Buffer clear bitr 20 1 TXIE Transmit interrupt enable bit 15 1 EN SPI n Enable register 0x10 32 read-write n 0x0 0xFF ENABLE SPI ENABLE bit 0 1 LR SPI n delay Length Register 0x14 32 read-write n 0x10101 0xFFFFFFFF BTL Burst delay length 8 8 SPL Stop delay length 16 8 STL Start delay length 0 8 RDR SPI n Receive Data Register 0x0 32 read-only n 0x0 0xFFFF RDR Data 0 17 SR SPI n Status Register 0x8 32 read-write n 0x6 0xFFFF OVRF receive overrun error flag 4 1 read-write RRDY receive buffer ready flag 0 1 read-only RXDMAF DMA receive Operation complete flag 8 1 read-write SBUSY Transmit/Receive Operation flag 7 1 read-only SRDY Shift register ready flag 2 1 read-only SSDET The rising edge of SS detect flag 6 1 read-write SSON SS signal status flag 5 1 read-write TRDY Transmit buffer empty flag 1 1 read-only TXDMAF DMA transmit Operation complete flag 9 1 read-write UDRF transmit underrun error flag 3 1 read-write TDR SPI n Transmit Data Register 0x0 32 write-only n 0x0 0xFFFF TDR Data 0 17 SP1 SERIAL PERIPHERAL INTERFACE SPI 0x40009100 0x0 0x100 registers n SPI1 33 BR SPI n Baud Rate Register 0xC 32 read-write n 0xFF 0xFFFF BR buadrate 0 16 CR SPI n Control Register 0x4 32 read-write n 0x0 0xFFFFFFFF BITSZ Transmit/receive Data bits select bit 0 2 CPHA SPI clock phase bit 3 1 CPOL SPI clock polarity bit 2 1 DRXIE DMA Rx Deone Interrupt enable bit 17 1 DTXIE DMA TX Done Interrupt enable bit 18 1 LBE Loop-back mode select bit in master mode 11 1 MS master/slaver select bit 5 1 MSBF MSB/LSB transmit select bit 4 1 RXBC Recieve buffer clear enable 19 1 RXIE Receive interrupt enable bit 14 1 SSCIE SSn Edge Chagne Interrupt enable bit 16 1 SSMASK SS Signal masking bit in slave mode 10 1 SSMO SS output signal select bit 9 1 SSMOD SS Auto/Manual Output select bit 13 1 SSOUT SS output signal select bit 12 1 SSPOL SS Signal polarity select bit 8 1 TXBC TX Buffer clear bitr 20 1 TXIE Transmit interrupt enable bit 15 1 EN SPI n Enable register 0x10 32 read-write n 0x0 0xFF ENABLE SPI ENABLE bit 0 1 LR SPI n delay Length Register 0x14 32 read-write n 0x10101 0xFFFFFFFF BTL Burst delay length 8 8 SPL Stop delay length 16 8 STL Start delay length 0 8 RDR SPI n Receive Data Register 0x0 32 read-only n 0x0 0xFFFF RDR Data 0 17 SR SPI n Status Register 0x8 32 read-write n 0x6 0xFFFF OVRF receive overrun error flag 4 1 read-write RRDY receive buffer ready flag 0 1 read-only RXDMAF DMA receive Operation complete flag 8 1 read-write SBUSY Transmit/Receive Operation flag 7 1 read-only SRDY Shift register ready flag 2 1 read-only SSDET The rising edge of SS detect flag 6 1 read-write SSON SS signal status flag 5 1 read-write TRDY Transmit buffer empty flag 1 1 read-only TXDMAF DMA transmit Operation complete flag 9 1 read-write UDRF transmit underrun error flag 3 1 read-write TDR SPI n Transmit Data Register 0x0 32 write-only n 0x0 0xFFFF TDR Data 0 17 T0 16-BIT TIMER TIMER 0x40003000 0x0 0x20 registers n TIMER0 5 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T1 16-BIT TIMER TIMER 0x40003020 0x0 0x20 registers n TIMER1 6 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T2 16-BIT TIMER TIMER 0x40003040 0x0 0x20 registers n TIMER2 7 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T3 16-BIT TIMER TIMER 0x40003060 0x0 0x20 registers n TIMER3 8 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T4 16-BIT TIMER TIMER 0x40003080 0x0 0x20 registers n TIMER4 9 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T5 16-BIT TIMER TIMER 0x400030A0 0x0 0x20 registers n TIMER5 10 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T6 16-BIT TIMER TIMER 0x400030C0 0x0 0x20 registers n TIMER6 11 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T7 16-BIT TIMER TIMER 0x400030E0 0x0 0x20 registers n TIMER7 12 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T8 16-BIT TIMER TIMER 0x40003100 0x0 0x20 registers n TIMER8 13 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 T9 16-BIT TIMER TIMER 0x40003120 0x0 0x20 registers n TIMER9 14 CNT Timer n Count Register 0x14 32 read-write n 0x0 0xFFFF CNT CNT 0 16 CR1 Timer n Control Register 1 0x0 32 read-write n 0x0 0xFFFF ADCTRGEN ADCTRGEN 8 1 CKSEL counter clock source select 4 3 CLRMD clear select when capture mode 2 2 CSYNC Synchronized clear counter with other synchronized timers 14 1 MODE Timer operatin mode control 0 2 OUTPOL Timer ouput Polarity 12 1 SSYNC Synchronized start counter with other synchronized timers 15 1 STARTLVL Timer output polarity control 7 1 UAO Select GRA, GRB update mode 13 1 CR2 Timer n Control Register 2 0x4 32 read-write n 0x0 0x3 TCLR Timer register clear 1 1 TEN Timer enable bit 0 1 GRA Timer n General Register A 0xC 32 read-write n 0x0 0xFFFF GRA GRA 0 16 GRB Timer n General Register B 0x10 32 read-write n 0x0 0xFFFF GRB GRB 0 16 IER Timer n Interrupt Enable Register 0x1C 32 read-write n 0x0 0xF MAIE GRA Match interrupt enablee 2 1 MBIE GRB Match interrupt enable 1 1 OVIE Counter overflow interrupt enable 0 1 PRS Timer n Prescaler Register 0x8 32 read-write n 0x0 0x3FF PRS Prescaler value of count clock 0 10 SR Timer n Status Register 0x18 32 read-write n 0x0 0x7 MFA Match register A Flag 2 1 MFB MATCH register B flag 1 1 OVF counter overflow falg 0 1 U0 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008000 0x0 0x100 registers n UART0 38 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decided by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 TXEIE End-of-transmit interrupt enable 3 1 IIR UART Interrupt ID Register 0x8 32 read-only n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 TXE Interrupt Status 4 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 read-only DR Data recevied 0 1 read-only FE frame error 3 1 read-only OE overrun error 1 1 read-only PE parity error 2 1 read-only TEMT Transmit empty 6 1 read-only THRE Transmit holding register empty 5 1 read-only RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 U1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008100 0x0 0x100 registers n UART1 39 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decided by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 TXEIE End-of-transmit interrupt enable 3 1 IIR UART Interrupt ID Register 0x8 32 read-only n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 TXE Interrupt Status 4 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 read-only DR Data recevied 0 1 read-only FE frame error 3 1 read-only OE overrun error 1 1 read-only PE parity error 2 1 read-only TEMT Transmit empty 6 1 read-only THRE Transmit holding register empty 5 1 read-only RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 U2 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008200 0x0 0x100 registers n UART2 40 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decided by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 TXEIE End-of-transmit interrupt enable 3 1 IIR UART Interrupt ID Register 0x8 32 read-only n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 TXE Interrupt Status 4 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 read-only DR Data recevied 0 1 read-only FE frame error 3 1 read-only OE overrun error 1 1 read-only PE parity error 2 1 read-only TEMT Transmit empty 6 1 read-only THRE Transmit holding register empty 5 1 read-only RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 U3 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER UART 0x40008300 0x0 0x100 registers n UART3 41 BDR Baud rate Divisor Latch Register 0x20 32 read-write n 0x0 0xFFFF BDR baudrate setting 0 16 BFR Baud rate Fraction Counter Register 0x24 32 read-write n 0x0 0xFF BFR Fraction counter value 0 8 DCR UART Data Control Register 0x10 32 read-write n 0x0 0xFF RXINV Rx Data Inversion selection 3 1 TXINV TX Data Inversion selection 2 1 IDTR Inter-frame Delay Time Register 0x30 32 read-write n 0x0 0xFF WAITVAL wait time is decided by this value 0 3 IER UART Interrupt Enable Register 0x4 32 read-write n 0x0 0xFF DRIE Data receive interrupt enable 0 1 DRXIEN DMA Receiver line status interrupt enable 4 1 DTXIEN DMA transmit done interrupt enable 5 1 RLSIE receiver line status interrupt enable 2 1 THREIE Transmit holding register empty interrupt enable 1 1 TXEIE End-of-transmit interrupt enable 3 1 IIR UART Interrupt ID Register 0x8 32 read-only n 0x0 0xFF IID Interrupt source ID 1 3 IPEN Interrupt pending bit 0 1 TXE Interrupt Status 4 1 LCR UART Line Control Register 0xC 32 read-write n 0x0 0xFF BREAK BREAK 6 1 DLEN Data length in one transfer word 0 2 PARITY PARITY 4 1 PEN parity bit transfer enable 3 1 STICKP STICK 5 1 STOPBIT STOPBIT 2 1 LSR UART Line Status Register 0x14 32 read-write n 0x60 0xFF BI break condition indication bit 4 1 read-only DR Data recevied 0 1 read-only FE frame error 3 1 read-only OE overrun error 1 1 read-only PE parity error 2 1 read-only TEMT Transmit empty 6 1 read-only THRE Transmit holding register empty 5 1 read-only RBR Receive Buffer Register 0x0 32 read-only n 0x0 0xFF RBR recevied/transmit data 0 8 THR Transmit Data Hold Register 0x0 32 write-only n 0x0 0xFF THR recevied/transmit data 0 8 WDT WATCH-DOG TIMER WDT 0x40000200 0x0 0x100 registers n WDT 3 CNT Watchdog Timer Current Counter Register 0x4 32 read-write n 0xFFFF 0xFFFFFFFF CON Watchdog Timer Control Register 0x8 32 read-write n 0x805C 0xFFFF CKSEL WDTCLKIN clock source select 3 1 WDBG WDT operation in debug mode 15 1 WDTEN WDT counter enable 4 1 WDTIE WDT interrupt enable 7 1 WDTRE WDT interrupt reset 6 1 WPRS counter prescaler 0 3 WUF WDT underflow falg 8 1 LR Watchdog Timer Load Register 0x0 32 read-write n 0x0 0xFFFFFFFF